The present invention relates to the use of thin-film deposition technology to create a high speed structure having high density interconnects formed on a conventional printed wiring board substrate. More specifically, the present invention pertains to an improved method for minimizing the effects of accumulated stress between the printed wiring board substrate and overlying deposited thin film layers while maintaining a relatively overall low impedance in the resulting structure. The method of the present invention is also useful for creating interconnections on high density daughter boards that carry packaged devices.
The semiconductor industry continues to produce integrated circuits of increasing complexity and increasing density. The increased complexity of some of these integrated circuits has, in turn, resulted in an increased number of input/output pads on the circuit chips. At the same time, the increased density of the chips has driven the input/output pad pitch downward. The combination of these two trends has been a significant increase in the connector pin wiring density needed to connect the chips to packages that interface with the outside world and interconnect the chips to other integrated circuit devices.
A number of different technologies have been developed to interconnect one or more integrated circuits and related components. One such technology is based on traditional printed wiring board (PWB) technology that found wide use during the period in which integrated circuits were packaged in surface mount devices like quad flat packs (QFPs). PWB technology typically uses copper and insulating dielectric material sub-laminates as building blocks to create the required interconnect structures. The process of forming a copper conductive pattern on the sub-laminate in PWB technology typically includes forming a dry film of photo resist over the copper layer, patterning and developing the photo resist to form an appropriate mask and selectively etching away the unwanted copper, thereby leaving the desired patterned conductive layer.
Substrates used in PWB technology can be manufactured in large area panels providing efficiencies that lower the costs of production. Interconnect solutions using this technology generally have relatively good performance characteristics because of the copper and low dielectric constant (e.g. less than or equal to 4.0) employed. The printed wiring board industry, however, has not kept pace with the advances in semiconductor manufacturing in terms of pad density and pad count. As a result, there is a capability gap between semiconductor manufacturers and interconnect printed wiring board manufactures.
In some applications, two or more pieces of laminate are laminated together to form a final structure. Interconnection between laminated layers can be provided by through-holes mechanically drilled and then plated. The drilling process is relatively slow and expensive and can require a large amount of board space. As the number of interconnect pads increases, an increased number of signal layers is often used to form the interconnect structure. Because of these limitations, the conventional printed wiring board technology needs to go to a large number of metal layers (e.g. greater than eight layers) for some of the applications in high density integrated circuit packaging and daughter board fabrication. Utilizing a large number of layers in this context generally increases cost and decreases electrical performance. Also, the pad size limits the wiring density on any given layer with this technology. Thus, PWB technology, while useful for some applications, is not capable of providing the connection density required in other applications.
To improve the interconnect density of PWB technology, an advanced printed wiring board technology approach called build-up multi-layer has been developed. In this technology a traditional printed wiring board core is the starting point. Standard drilling and plating techniques form plated through-holes in the core. From the basic core this build-up approach has many variations. Typically a dielectric layer approximately 50 microns thick is laminated to both the top and bottom major surfaces of the conventionally fabricated printed wiring board substrate. Vias are made in the build-up layer by laser ablation, photo mask/plasma etch, or other known methods. An electrodeless seeding step is then done prior to a panel plating step that metalizes both the upper and lower surfaces. Subsequent masking and wet etching steps then define a desired conductive pattern over the laminated dielectric layers.
This technology offers a large improvement in terms of density over standard PWB technology without build-up layers; however, such build-up boards require multiple layers in order to meet the developing high density packaging and daughter board requirements. Thus this technology still has limitations.
Another conventional approach used to package high density interconnect applications uses cofired ceramic substrates and is referred to generally as multilayer ceramic or MLC technology. Basically, MLC technology involves rolling a ceramic mix into sheets, drying the sheets, punching vias, screening the rolled sheets with a metal paste representing the trace pattern on the surface of the ceramic, stacking and laminating all the layers together, then cofiring at a high temperature (e.g. greater than 850.degree. C.) to achieve the desired interconnections.
MLC construction has found extensive use in high density and high reliability products where the robustness of the high density interconnect package outweighs the cost considerations. The ability to create a hermetic seal in the ceramic improves the ability to withstand environments not tolerable to conventional printed wiring board technology. While this technology is capable of high density packaging applications (e.g. greater than 1000 pads), it is also very costly. Additionally, performance characteristics, such as signal propagation time, are impacted due to the relatively high dielectric constant (e.g. between 5.0 and 9.0) of the ceramic material. MLC technology provides higher connection density than PWB technology, but is not capable of providing the connection density required for some of today's high density interconnect applications.
A third approach which the high density interconnect and packaging industry has moved to addressing these high density interconnect applications using thin film deposition technology. This is sometimes referred to as deposited on laminate or D/L technology in a broad sense, as well as MCM-D or MCM deposition technology in a multichip module context. In some applications, such D/L technology includes forming and patterning thin film conductive traces over large substrates such as the laminated printed wiring boards discussed above. Such large substrates may have a surface area of 40 centimeters by 40 centimeters or more, thereby providing efficiencies that lower the costs of production.
D/L technology utilizes a combination of low cost printed wiring board structures, with or without the use of the build-up multi-layers on the printed wiring board, as a starting point to meet the high density and low cost interconnect requirements. This combination of existing conventional high volume printed wiring board technology and advanced thin film deposition technology represents a significant economic advantage and density improvement as compared to the previously discussed PWB and MLC technologies.
One significant feature of D/L technology is that it creates a high interconnect density substrate using thin film processes on only one side of the printed wiring board. The high density interconnects are formed by depositing alternating insulating and conducting thin film layers. The total thickness of several of these deposited layers is less than the thickness of a single traditional build-up layer. This eliminates the need for balancing the build-up layers on both top and bottom to prevent warpage of the substrate.
The D/L process involves first laying down a layer of an insulating dielectric on the top surface of a printed wiring board substrate, depositing a conductive material over the dielectric layer, creating a circuit pattern in the conductive material, then depositing the next insulating and conductive layers. The various layers so created are connected through vias constructed using a variety of known techniques such as wet chemical etch, photo expose and develop or laser ablation. In this way a three dimensional deposited laminated structure is achieved enabling high density interconnect patterns to be fabricated in small physical areas.
Despite the definite advantages of D/L technology, there are potential problems that may result in failure modes and performance limitations if the overlying deposited thin film layers are not properly implemented. One important aspect of the implementation of deposited thin film layers on the surface of printed wiring board substrates is the control of mechanical stresses generated by both processing and operation. Key to control of the these stresses is understanding their sources and providing methods and structures that minimize them.
The stresses in a high density interconnect structure result from a number of sources. These sources include differences in the coefficients of thermal expansion between dielectric, laminate and conductive materials, physical handling, and water vapor absorbed by the polymers of the dielectric materials in both the printed wiring board substrate and the deposited thin film build-up layers. Each of these stresses can be a source of failures such as cracking of the dielectric material and cracking and delamination of the conductive material. In either of these cases opens and shorts can destroy the functionality of the completed high density interconnect structure. The stresses associated with physical handling can be substantially eliminated through proper design of processes, operator training, and proper fixture design. Stresses related to thermal changes, however, must be minimized through proper design of the high density interconnect structure.
The stresses linked to thermal changes occur for several reasons, but the result is that stress accumulates at the interfaces between the metal conducting features and the surrounding dielectric of the high density interconnect structure. If enough stress accumulates a crack will develop that, if uninterrupted, may propagate through the overlying deposited thin film layers creating failures. One attempt to reduce the stress included adding a filler to the dielectric layer when being deposited. The filler acted to increase the durability of the dielectric layer when subjected to stresses resulting from thermal mismatch in the materials, by decreasing the brittleness of the same. Typical fillers include silica compounds, such as silicon dioxide, silica glass and the like. In addition rubber compounds may be employed as fillers. A problem encountered with increasing the filler content of the dielectric layer is that the dielectric constant is proportional to the amount of filler included in the layer. As a result, the less durable the dielectric layer, the higher the impedance associated with the structure formed with such a layer.
What is needed, therefore, is a low-impedance high-density deposited-on-laminate structure having reduced stress.